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mc145554 ? mc145557 ? MC145564 ? mc145567 motorola 1
the mc145554, mc145557, MC145564, and mc145567 are all per channel pcm c odecfilters . t hes e d evices p erfor m t h e v oic e d igitizatio n a nd reconstruction as well as the band limiting and smoothing required for pcm systems. they are designed to operate in both synchronous and asynchronous applications a n d c ontai n a n o nchi p p recisio n v oltag e r eference. t he mc145554 (mulaw) and mc145557 (alaw) are general purpose devices that are of fered in 16pin packages. the MC145564 (mulaw) and mc145567 (alaw), of fered in 20pin packages, add the capability of analog loopback and pushpull power amplifiers with adjustable gain. these devices have an input operational amplifier whose output is the input to the encoder section. the encoder section immediately lowpass filters the analog signal with an active rc filter to eliminate veryhighfrequency noise from being modulated down to the pass band by the switched capacitor filter . from the active rc filter , the analog signal is converted to a dif ferential signal. from this point, all analog signal processing is done dif ferentially . this allows processing o f a n a nalo g s igna l t ha t i s t wic e t h e a mplitud e a llowe d b y a singleended d esign , w hic h r educe s t h e s ignificanc e o f n ois e t o b oth t he inverted and noninverted signal paths. another advantage of this dif ferential design is that noise injected via the power supplies is a commonmode signal that is cancelled when the inverted and noninverted signals are recombined. this dramatically improves the power supply rejection ratio. after the dif ferential converter , a dif ferential switched capacitor filter band passes the analog signal from 200 hz to 3400 hz before the signal is digitized by the differential compressing a/d converter. the d ecode r a ccept s p c m d at a a n d e xpand s i t u sin g a d ifferentia l d /a converter. the output of the d/a is lowpass filtered at 3400 hz and sinx/x compensated by a dif ferential switched capacitor filter . the signal is then filtered by an active rc filter to eliminate the outofband energy of the switched capacitor filter. these pcm codecfilters accept both longframe and shortframe industry standard clock formats. they also maintain compatibility with motorola's family of tsacs and mc3419/mc34120 slic products. the mc145554/57/64/67 family of pcm codecfilters utilizes cmos due to its r eliabl e l owpowe r p erformanc e a n d p rove n c apabilit y f or c omplex analog/digital vlsi functions. mc145554/57 (16pin package) ? fully differential analog circuit design for lowest noise ? performance specified for extended temperature range of 40 to + 85 c ? transmit bandpass and receive lowpass filters onchip ? active rc prefiltering and postfiltering ? mulaw companding mc145554 ? alaw companding mc145557 ? onchip precision voltage reference (2.5 v) ? typical power dissipation of 40 mw, power down of 1.0 mw at 5 v MC145564/67 (20pin package) e all of the features of the mc145554/57 plus: ? mulaw companding MC145564 ? alaw companding mc145567 ? pushpull power drivers with external gain adjust ? analog loopback order this document by mc145554/d semiconductor technical data l suffix ceramic package case 620 mc145554/57 p suffix plastic dip case 648 mc145554/57 16 1 16 1 20 1 l suffix ceramic package case 732 MC145564/67 20 1 p suffix plastic dip case 738 MC145564/67 dw suffix sog package case 751g mc145554/57 dw suffix sog package case 751d MC145564/67 16 1 20 1 ? motorola, inc. 1995 rev 1 9/95 (replaces adi1517)
mc145554 ? mc145557 ? MC145564 ? mc145567 motorola 2 pin assignments mc145554, mc145557 MC145564, mc145567 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 ts x gs x vf x i mclk x bclk x d x v cc vf r o gnda mclk r / pdn bclk r / clksel d r fs r v bb vf x i + fs x vpi vpo gnda vpo + 5 4 3 2 1 10 9 8 7 6 14 15 16 17 18 19 20 11 12 13 anlb v bb ts x mclk x bclk x d x fs x gs x vf x i vf x i + v cc vf r o mclk r / pdn bclk r / clksel d r fs r functional block diagram * MC145564 and mc145567 only. gs x anlb * v cc gnda v bb fs x fs r mclk x bclk x mclk r / pdn bclk r / clksel ts x d x d r receive shift reg receive latch mux s/h 5pole sc lowpass filter rc active lowpass filter vf r o vpi * 1 vpo * vpo + * vf x i + vf x i 8 4 8 sar reg transmit shift reg 4 cdac rdac bandgap voltage ref comp rc active lowpass filter 5pole sc lowpass filter 3pole highpass and s/h internal sequencing and control + +
mc145554 ? mc145557 ? MC145564 ? mc145567 motorola 3 device description a codecfilter is used for digitizing and reconstructing the human voice. these devices were developed primarily for the telephone network to facilitate voice switching and trans- mission. once the voice is digitized, it may be switched by digital switching methods or transmitted long distance (t1, microwave, satellites, etc.) without degradation. the name codec is an acronym from acodero (for the a/d used to digi - tize voice) and adecodero (for the d/a used for reconstruct - ing voice). a codec is a single device that does both the a/d and d/a conversions. to digitize intelligible voice requires a signaltodistortion ratio of about 30 db over a dynamic range of about 40 db. this can be accomplished with a linear 13bit a/d and d/a, but will far exceed the required signaltodistortion ratio at amplitudes greater than 40 db below the peak amplitude. this excess performance is at the expense of data per sam- ple. m ethod s o f d ata r eductio n a r e i mplemente d b y c om- pressin g t h e 1 3bi t l inea r s chem e t o c ompande d 8 bit schemes . t here a r e t w o c ompandin g s cheme s u sed: mu25 5 l a w s pecifically i n n ort h a merica , a n d a law specifically i n e urope . t hes e c ompandin g s cheme s a re accepted world wide. these companding schemes follow a segmented or apiecewiselinearo curve formatted as sign bit, three chord bits, and four step bits. for a given chord, all six- teen of the steps have the same voltage weighting. as the voltage of the analog input increases, the four step bits incre - ment a n d c arr y t o t h e t hre e c hor d b it s w hic h i ncrement. when t h e c hor d b it s i ncrement , t h e s te p b it s d oubl e t heir voltage weighting. this results in an ef fective resolution of six bits (sign + chord + four step bits) across a 42 db dynamic range ( seve n c hord s a bov e z ero , b y 6 d b p e r c hord). tables 3 and 4 show the linear quantization levels to pcm words for the two companding schemes. in a s amplin g e nvironment , n yquis t t heor y s ay s t ha t t o properly sample a continuous signal, it must be sampled at a frequency higher than twice the signal' s highest frequency component. v oice contains spectral energy above 3 khz, but its absence is not detrimental to intelligibility . t o reduce the digital data rate, which is proportional to the sampling rate, a sample rate of 8 khz was adopted, consistent with a band - width of 3 khz. this sampling requires a lowpass filter to limit the high frequency energy above 3 khz from distorting the i nban d s ignal . t h e t elephon e l in e i s a ls o s ubjec t t o 50/60 hz power line coupling, which must be attenuated from the signal by a highpass filter before the a/d converter. the d/a process reconstructs a staircase version of the desired inband signal, which has spectral images of the in band signal modulated about the sample frequency and its harmonics. these spectral images, called aliasing compo - nents, need to be attenuated to obtain the desired signal. the lowpass filter used to attenuate these aliasing compo - nents is typically called a reconstruction or smoothing filter. the m c145554/57/64/6 7 p c m c odecfilter s h av e t he codec, b ot h p resamplin g a n d r econstructio n f ilters , a nd a precision voltage reference onchip, and require no external components. pin description digital fs r receive frame sync this is an 8 khz enable that must be synchronous with bclk r . following a rising fs r edge, a serial pcm word at d r is clocked by bclk r into the receive data register . fs r also initiates a decode on the previous pcm word. in the ab - sence of fs x , the length of the f s r pulse is used to deter - mine whether the i/o conforms to the short frame sync or long frame sync convention. d r receive digital data input bclk r /clksel receive data clock and master clock frequency selector if this input is a clock, it must be between 128 khz and 4.096 m hz , a n d s ynchronou s w it h f s r . i n s ynchronous applications this pin may be held at a constant level; then bclk x is used as the data clock for both the transmit and receive sides, and this pin selects the assumed frequency of the master clock (see table 1 in functional description ). mclk r /pdn receive master clock and powerdown control because of the shared dac architecture used on these devices, only one master clock is needed. whenever fs x is clocking, mclk x is used to derive all internal clocks, and the mclk r /pdn pin merely serves as a powerdown control. if mclk r /pdn pin is held low or is clocked (and at least one of the frame syncs is present), the part is powered up. if this pin is held high, the part is powered down. if f s x is absent but f s r is still clocking, the device goes into receive half channel m ode , a n d m clk r ( i f c locking ) g enerate s t he internal clocks. mclk x transmit master clock this clock is used to derive the internal sequencing clocks; it must be 1.536 mhz, 1.544 mhz, or 2.048 mhz. bclk x transmit data clock bclk x m a y b e a ny f requenc y b etwee n 1 2 8 k h z a nd 4.096 mhz, but it should be synchronous with mclk x . d x transmit digital data output this output is controlled by fs x and bclk x to output the pcm data word; otherwise this pin is in a highimpedance state. fs x transmit frame sync this is an 8 khz enable that must be synchronous with bclk x . a rising f s x edge initiates the transmission of a
mc145554 ? mc145557 ? MC145564 ? mc145567 motorola 4 serial pcm word, clocked by b clk x , out of d x . if the f s x pulse is high for more than eight b clk x periods, the d x and ts x outputs will remain in a lowimpedance state until fs x is brought low. the length of the fs x pulse is used to deter- mine whether the transmit and receive digital i/o conforms to the short frame sync or to the long frame sync conven - tion. ts x transmit time slot indicator this is an opendrain output that goes low whenever the d x output is in a lowimpedance state (i.e., during the trans - mit time slot when the pcm word is being output) for en - abling a pcm bus driver. anlb analog loopback control input (MC145564/67 only) when held high, this pin causes the input of the transmit rc active filter to be disconnected from gs x and connected to vpo + for analog loopback testing. this pin is held low in normal operation. analog gs x gainsetting transmit this output of the transmit gainadjust operational amplifi - er i s i nternall y c onnecte d t o t h e e ncode r s ectio n o f t he device. it must be used in conjunction with vf x i and vf x i+ to set the transmit gain for a maximum signal amplitude of 2.5 v peak. this output can drive a 600 w load to 2.5 v peak. vf x i voicefrequency transmit input (inverting) this i s t h e i nvertin g i npu t o f t h e t ransmi t g ainadjust operational amplifier. vf x i+ voicefrequency transmit input (noninverting) this is the noninverting input of the transmit gainadjust operational amplifier. vf r o voicefrequency receive output this receive analog output is capable of driving a 600 w load to 2.5 v peak. vpi voltage power input (MC145564/67 only) this is the inverting input to the first receive power ampli - fier. both of the receive power amplifiers can be powered down by connecting this input to v bb . vpo voltage power output (inverted) (MC145564/67 only) this inverted output of the receive pushpull power ampli- fiers can drive 300 w to 3.3 v peak. vpo+ voltage power output (noninverted) (mc145554/67 only) this noninverted output of the receive pushpull power amplifier pair can drive 300 w to 3.3 v peak. power supply gnda analog ground this terminal is the reference level for all signals, both ana - log and digital. it is 0 v. v cc positive power supply v cc is typically 5 v. v bb negative power supply v bb is typically 5 v. functional description analog interface and signal path the transmit portion of these codecfilters includes a low noise gain setting amplifier capable of driving a 600 w load. its output is fed to a threepole antialiasing prefilter . this prefilter i ncorporate s a t wopole b utterwort h a ctiv e l ow pass filter , and a single passive pole. this prefilter is fol - lowed b y a s ingl e e ndedtodifferentia l c onverte r t ha t i s clocked at 256 khz. all subsequent analog processing uti - lizes fully dif ferential circuitry . the next section is a fullydif - ferential, fivepole switched capacitor lowpass filter with a 3.4 khz passband. after this filter is a 3pole switchedca - pacitor highpass filter having a cutof f frequency of about 200 hz. this highpass stage has a transmission zero at dc that eliminates any dc coming from the analog input or from accumulated operational amplifier of fsets in the preceding fil - ter stages. the last stage of the highpass filter is an auto - zeroed sample and hold amplifier. one bandgap voltage reference generator and digitalto analog c onverte r ( dac ) a r e s hare d b y t h e t ransmit a nd receive sections. the autozeroed, switchedcapacitor band- gap reference generates precise positive and negative refer - ence v oltage s t ha t a r e i ndependent o f t emperatur e a nd power s uppl y v oltage . a b inaryweighte d c apacito r a rray (cdac) forms the chords of the companding structure, while a resistor string (rdac) implements the linear steps within each chord. the encode process uses the dac, the voltage reference, and a framebyframe autozeroed comparator to implement a s uccessiveapproximatio n c onversion a lgo- rithm. a l l o f t h e a nalo g c ircuitr y i nvolve d i n t h e d at a c on- versio n e t h e v oltag e r eference , r dac , c dac , a nd comparator e are implemented with a dif ferential architec - ture. the receive section includes the dac described above, a sample a n d h ol d a mplifier , a f ivepole 3 40 0 h z s witched capacitor lowpass filter with sinx/x correction, and a two pole a ctiv e s moothin g f ilte r t o r educ e t h e s pectra l c om- ponents of the switched capacitor filter . the output of the smoothing filter is a power amplifier that is capable of driving a 600 w load. the MC145564 and mc145567 add a pair of power amplifiers that are connected in a pushpull configu - ration; t w o e xterna l r esistor s s e t t he g ai n o f b ot h o f t he
mc145554 ? mc145557 ? MC145564 ? mc145567 motorola 5 complementary outputs. the output of the second amplifier may be internally connected to the input of the transmit anti aliasing filter by bringing the anlb pin high. the power am - plifiers c an d riv e u nbalance d 3 00 w l oad s o r a b alanced 600 w load; they may be powered down independent of the rest of the chip by tying the vpi pin to v bb . master clocks since the codecfilter design has a single dac architec - ture, only one master clock is used. in normal operation (both frame syncs clocking), the mclk x is used as the master clock, regardless of whether the mclk r / pdn pin is clocking or low . the same is true if the part is in transmit halfchannel mode (fs x clocking, fs r held low). but if the codecfilter is in the receive halfchannel mode, with fs r clocking and fs x held low, mclk r is used for the internal master clock if it is clocking; if mclkr is low , then m clk x is still used for the internal master clock. since only one of the master clocks is used at any given time, they need not be synchronous. the m aste r c loc k f requenc y m us t b e 1 .53 6 m hz, 1.544 mhz, or 2.048 mhz. the frequency that the codec filter expects depends upon whether the part is a mulaw or an alaw part, and on the state of the b clk r /clksel pin. the allowable options are shown in t able 1. when a level (rather than a clock) is provided for b clk r /clksel, b clk x is used as the bit clock for both transmit and receive. table 1. master clock frequency determination bclk r /clksel master clock frequency expected bclk r /clksel mc145554/64 mc145557/67 clocked, 1, or open 1.536 mhz 1.544 mhz 2.048 mhz 0 2.048 mhz 1.536 mhz 1.544 mhz frame syncs and digital i/o these codecfilters can accommodate both of the industry standard t imin g f ormats . t h e l on g f ram e s yn c m od e i s used by motorola' s mc145500 family of codecfilters and the udlt family of digital loop transceivers. the short frame sync mode is compatible with the idl (interchip digital link) serial format used in motorola' s isdn family and by other companies i n t hei r t elecommunicatio n d evices . t hese codecfilters use the length of the transmit frame sync (fs x ) to determine the timing format for both transmit and receive unless t h e p ar t i s o peratin g i n t h e r eceiv e h alfchannel mode. in t h e l on g f ram e s yn c m ode , t h e f ram e s yn c p ulses must be at least three bit clock periods long. the d x and t s x outputs a r e e nable d b y t h e l ogica l a ndin g o f f s x a nd bclk x ; when both are high, the sign bit appears at the d x output. the next seven rising edges of bclk x clock out the remaining seven bits of the pcm word. the d x and t s x out- puts return to a high impedance state on the falling edge of the eighth bit clock or the falling edge of f s x , whichever comes later . the receive pcm word is clocked into d r on the eight falling bclk r edges following an fs r rising edge. for short frame sync operation, the frame sync pulses must be one bit clock period long. on the first bclk x rising edge after the falling edge of bclk x has latched fs x high, the d x and t s x outputs are enabled and the sign bit is pres - ented on d x . the next seven rising edges of b clk x clock out the remaining seven bits of the pcm word; on the eighth bclk x falling edge, the d x and t s x outputs return to a high impedance state. on the second falling b clk r edge follow- ing an f s r rising edge, the receive sign bit is clocked into d r . the next seven b clk r falling edges clock in the re - maining seven bits of the receive pcm word. table 2 shows the coding format of the transmit and re - ceive pcm words. halfchannel modes in addition to the normal fullduplex operating mode, these codecfilters can operate in both transmit and receive half channel modes. t ransmit halfchannel mode is entered by holding f s r low . the v f r o output goes to analog ground but remains in a low impedance state (to facilitate a hybrid interface); pcm data at d r is ignored. holding f s x low while clocking fs r puts these devices in the receive halfchannel mode. in this state, the transmit input operational amplifier continues to operate, but the rest of the transmit circuitry is disabled; the d x and t s x outputs remain in a high imped- ance state. m clk r is used as the internal master clock if it is clocking. if mclk r is not clocking, then mclk x is used for the internal master clock, but in that case it should be syn - chronous with fs r . if bclk r is not clocking, b clk x will be used for the receive data, just as in the fullchannel operat - ing mode. in receive halfchannel mode only , the length of the f s r pulse is used to determine whether short frame sync or long frame sync timing is used at d r . powerdown holding both fs x and fs r low causes the part to go into the powerdown state. powerdown occurs approximately 2 ms after the last frame sync pulse is received. an alterna - tive way to put these devices in powerdown is to hold the mclk r /pdn pin high. when the chip is powered down, the d x , ts x , and gs x outputs are high impedance, the v f r o, vpo, and vpo + operational amplifiers are biased with a trickle current so that their respective outputs remain stable at analog ground. t o return the chip to the powerup state, mclk r /pdn must be low or clocking and at least one of the frame sync pulses must be present. the d x and t s x outputs will remain in a highimpedance state until the second fs x pulse after powerup. table 2. pcm data format level mulaw (mc145554/64) alaw (mc145557/67) level sign bit chord bits step bits sign bit chord bits step bits + full scale 1 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 + zero 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 zero 0 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 full scale 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0
mc145554 ? mc145557 ? MC145564 ? mc145567 motorola 6 maximum ratings (voltage referenced to gnda) rating symbol value unit dc supply voltage v cc to v bb v cc to gnda v bb to gnda 0.5 to + 13 0.3 to + 7.0 7.0 to + 0.3 v v oltage on any analog input or output pin v bb 0.3 to v cc + 0.3 v v oltage on any digital input or output pin gnda 0.3 to v cc + 0.3 v operating temperature range t a 40 to + 85 c storage temperature range t stg 85 to + 150 c power supply (t a = 40 to + 85 c) characteristic min typ max unit dc supply voltage v cc v bb 4.75 4.75 5.0 5.0 5.25 5.25 v active power dissipation (no load) mc145554/57 MC145564/67 MC145564/67, vpi = v bb e e e 40 45 40 60 70 60 mw powerdown dissipation (no load) mc145554/57 MC145564/67 MC145564/67, vpi = v bb e e e 1.0 2.0 1.0 3.0 5.0 3.0 mw digital levels (v cc = 5 v 5%, v bb = 5 v 5%, gnda = 0 v, t a = 40 to + 85 c) characteristic symbol min max unit input low voltage v il e 0.6 v input high voltage v ih 2.2 e v output low voltage d x or ts x , i ol = 3.2 ma v ol e 0.4 v output high voltage d x , i oh = 3.2 ma i oh = 1.6 ma v oh 2.4 v cc 0.5 e e v input low current gnda v in v cc i il 10 + 10 m a input high current gnda v in v cc i ih 10 + 10 m a output current in high impedance state gnda d x v cc i oz 10 + 10 m a this device contains circuitry to protect against damage due to high static voltages or electric fields; however , it is advised that normal precautions be taken to avoid appli - cation of any voltage higher than maximum rated voltages to this high impedance circuit. for proper operation it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd . unused inputs must always be tied to an appropriate logic voltage level (e.g., v bb , gnda, or v cc ).
mc145554 ? mc145557 ? MC145564 ? mc145567 motorola 7 analog electrical characteristics (v cc = + 5 v 5%, v bb = 5 v 5%, vf x i connected to gs x , t a = 40 to + 85 c) characteristic min typ max unit input current ( 2.5 v in + 2.5 v) vf x i +, vf x i e 0.05 0.2 m a ac input impedance to gnda (1 khz) vf x i +, vf x i 10 20 e m w input capacitance vf x i +, vf x i e e 10 pf input offset voltage of gs x op amp vf x i +, vf x i e e 25 mv input common mode voltage range vf x i +, vf x i 2.5 e 2.5 v input common mode rejection ratio vf x i +, vf x i e 65 e db unity gain bandwidth of gs x op amp (r load 10 k w ) e 1000 e khz dc open loop gain of gs x op amp (r load 10 k w ) 75 e e db equivalent input noise (cmessage) between vf x i+ and vf x i at gs x e 20 e dbrnc0 output load capacitance for gs x op amp 0 e 100 pf output voltage range for gs x r load = 10 k w to gnda r load = 600 w to gnda 3.5 2.8 e e + 3.5 + 2.8 v output current ( 2.8 v v out + 2.8 v) gs x , vf r o 5.0 e e ma output impedance vf r o (0 to 3.4 khz) e 1 e w output load capacitance for vf r o 0 e 500 pf vf r o output dc offset voltage referenced to gnda e e 100 mv transmit power supply rejection positive, 0 to 100 khz, cmessage negative, 0 to 100 khz, cmessage 45 45 e e e e dbc receive power supply rejection positive, 0 to 100 khz, cmessage positive, 4 khz to 25 khz positive, 25 khz to 50 khz negative, 0 to 100 khz, cmessage negative, 4 khz to 25 khz negative, 25 khz to 50 khz 50 50 43 50 45 38 e e e e e e e e e e e e dbc db db dbc db db MC145564/67 power drivers input current ( 1 v vpi + 1 v) vpi e 0.05 0.5 m a input resistance ( 1 v vpi + 1 v) vpi 5 10 e m w input offset voltage (vpi connected to vpo) vpi e e 50 mv output resistance, inverted unity gain vpo+ or vpo e 1 e w unity gain bandwidth, open loop vpo e 400 e khz load capacitance ( w r load 300 w ) vpo+ or vpo to gnda 0 e 1000 pf gain from vpo to vpo+ (r load = 300 w , vpo+ to gnda level at vpo = 1.77 vrms, +3 dbm0) e 1 e v/v maximum 0 dbm0 level for better than 0.1 db linearity over the r load = 600 w range 10 dbm0 to + 3 dbm0 (for r load between vpo+ r load = 1200 w and vpo) r load = 10 k w 3.3 3.5 4.0 e e e e e e vrms power supply rejection of v cc or v bb (vpo connected to vpi) 0 to 4 khz vpo + or vpo to gnda 4 to 50 khz 55 35 e e e e db dif ferential power supply rejection of v cc or v bb (vpo connected to vpi) vpo+ to vpo, 0 to 50 khz 50 e e db
mc145554 ? mc145557 ? MC145564 ? mc145567 motorola 8 analog transmission performance (v cc = + 5 v 5%, v bb = 5 v 5%, gnda = 0 v, 0 dbm0 = 1.2276 vrms = + 4 dbm @ 600 w , fs x = fs r = 8 khz, bclk x = mclk x = 2.048 mhz synchronous operation, vf x i connected to gs x , t a = 40 to + 85 c unless otherwise noted) characteristic endtoend a/d d/a unit characteristic min max min max min max unit absolute gain (0 dbm0 @ 1.02 khz, t a = 25 c, v cc = 5 v, v bb = 5 v) e e 0.25 0.25 0.25 + 0.25 db absolute gain variation with temperature 0 to 70 c 40 to + 85 c e e e e e e 0.03 0.06 e e 0.03 0.06 db absolute gain variation with power supply (v cc = 5 v, 5%, v bb = 5 v, 5%) e e e 0.02 e 0.02 db gain vs level t one (relative to 10 dbm0, 1.02 khz) + 3 to 40 dbm0 40 to 50 dbm0 50 to 55 dbm0 0.4 0.8 1.6 + 0.4 + 0.8 + 1.6 0.2 0.4 0.8 + 0.2 + 0.4 + 0.8 0.2 0.4 0.8 + 0.2 + 0.4 + 0.8 db gain vs level pseudo noise ccitt g.712 10 to 40 dbm0 (mc145557/67 alaw relative to 10 dbm0) 40 to 50 dbm0 50 to 55 dbm0 e e e e e e 0.25 0.30 0.45 + 0.25 + 0.30 + 0.45 0.25 0.30 0.45 + 0.25 + 0.30 + 0.45 db total distortion, 1.02 khz tone (cmessage) + 3 dbm0 0 to 30 dbm0 40 dbm0 45 dbm0 55 dbm0 33 35 29 24 15 e e e e e 33 36 30 25 15 e e e e e 33 36 30 25 15 e e e e e dbc t otal distortion with pseudo noise ccitt g.714 3 dbm0 (mc145557/67 alaw) 6 to 27 dbm0 34 dbm0 40 dbm0 55 dbm0 27.5 35 33.1 28.2 13.2 e e e e e 28 35.5 33.5 28.5 13.5 e e e e e 28.5 36 34.2 30 15 e e e e e db idle channel noise (for endend and a/d, note 1) (mc145554/64 mulaw, cmessage weighted) (mc145557/67 alaw, psophometric weighted) e e 15 70 e e 15 70 e e 7 83 dbrnc0 dbm0p frequency response (relative to 1.02 khz @ 0 dbm0) 15 hz 50 hz 60 hz 200 hz 300 to 3000 hz 3300 hz 3400 hz 4000 hz 4600 hz e e e e 0.3 0.70 1.6 e e 40 30 26 e 0.3 + 0.3 0 28 60 e e e 1.0 0.15 0.35 0.8 e e 40 30 26 0.4 + 0.15 + 0.15 0 14 32 0.15 0.15 0.15 0.15 0.15 0.35 0.8 e e 0 0 0 0 + 0.15 + 0.15 0 14 30 db inband spurious 300 to 3000 hz (1.02 khz @ 0 dbm0, transmit and receive) e 48 e 48 e 48 dbm0 outofband spurious at vf r o (300 3400 hz @ 0 dbm0 in) 4600 to 7600 hz 7600 to 8400 hz 8400 to 100,000 hz e e e 30 40 30 e e e e e e e e e 30 40 30 db idle channel noise selective (8 khz, input = gnda, 30 hz bandwidth) e 70 e e e 70 dbm0 absolute delay (1600 hz) e e e 315 e 215 m s group delay referenced to 1600 hz 500 to 600 hz 600 to 800 hz 800 to 1000 hz 1000 to 1600 hz 1600 to 2600 hz 2600 to 2800 hz 2800 to 3000 hz e e e e e e e e e e e e e e e e e e e e e 220 145 75 40 75 105 155 40 40 40 30 e e e e e e e 90 125 175 m s crosstalk of 1020 hz @ 0 dbm0 from a/d or d/a (note 2) e e e 75 e 75 db intermodulation distortion of t wo frequencies of amplitudes 4 to 21 dbm0 from the range 300 to 3400 hz e 41 e 41 e 41 db notes: 1. extrapolated from a 1020 hz @ 50 dbm0 distortion measurement to correct for encoder enhancement. 2. selectively measured while the a/d is stimulated with 2667 hz @ 50 dbm0.
mc145554 ? mc145557 ? MC145564 ? mc145567 motorola 9 digital switching characteristics (v cc = 5 v 5%, v bb = 5 v 5%, gnda = 0 v, all signals referenced to gnda; t a = 40 to + 85 c, c load = 150 pf unless otherwise noted) characteristic symbol min typ max unit master clock frequency mclk x or mclk r f m e e e 1.536 1.544 2.048 e e e mhz minimum pulse width high or low mclk x or mclk r t w(m) 100 e e ns minimum pulse width high or low bclk x or bclk r t w(b) 50 e e ns minimum pulse width low fs x or fs r t w(fl) 50 e e ns rise time for all digital signals t r e e 50 ns fall time for all digital signals t f e e 50 ns bit clock data rate bclk x or bclk r f b 128 e 4096 khz setup time from bclk x low to mclk r high t su(brm) 50 e e ns setup time from mclk x high to bclk x low t su(mfb) 20 e e ns hold time from bclk x (bclk r ) low to fs x (fs r ) high t h(bf) 20 e e ns setup time for fs x (fs r ) high to bclk x (bclk r ) low for long frame t su(fb) 80 e e ns delay time from bclk x high to d x data valid t d(bd) 20 60 140 ns delay time from bclk x high to ts x low t d(bts) 20 50 140 ns delay time from the 8th bclk x low of fs x low to d x output disabled t d(zc) 50 70 140 ns delay time to valid data from fs x or bclk x , whichever is later t d(zf) 20 60 140 ns setup time from d r valid to bclk x low t su(db) 0 e e ns hold time from bclk r low to d r invalid t h(bd) 50 e e ns setup time from fs x (fs r ) high to bclk x (bclk r ) low in short frame t su(f) 50 e e ns hold time from bclk x (bclk r ) low to fs x (fs r ) low in short frame t h(f) 50 e e ns hold time from 2nd period of bclk x (bclk r ) low to fs x (fs r ) low in long frame t h(bfi) 50 e e ns
mc145554 ? mc145557 ? MC145564 ? mc145567 motorola 10 ts x t d(bts) t w(m) t w(m) t d(zc) mclk x mclk r bclk x t h(bf) t su(f) t h(f) t d(bd) t su(brm) t w(b) t w(b) 1 2 3 4 5 6 8 9 fs x d x t d(zc) msb ch1 ch2 ch3 st1 st2 st3 lsb bclk r t h(bf) t su(f) t h(f) fs r d r 1 2 3 4 5 6 7 8 9 msb ch1 ch2 ch3 st1 st2 st3 lsb t su(db) t h(bd) t h(bd) 7 t su(mfb) figure 1. short frame sync timing
mc145554 ? mc145557 ? MC145564 ? mc145567 motorola 11 mclk x mclk r t su(brm) t su(mfb) bclk x 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 t h(bf) t su(fb) t h(bfi) fs x t d(zf) t d(zf) t d(bd) t d(zc) t d(zc) d x msb ch1 ch2 ch3 st1 st2 st3 lsb msb ch1 ch2 ch3 st1 st2 st3 lsb bclk r t h(bf) t h(bfi) fs r d r t su(db) t h(bd) t h(bd) t su(fb) figure 2. long frame sync timing
mc145554 ? mc145557 ? MC145564 ? mc145567 motorola 12 5 v 1 2 3 4 5 6 7 8 mclk r / pdn bclk r / clksel d r fs r v cc vf r o gnda v bb analog out + 5 v 16 15 14 13 12 11 10 9 analog in tx time slot vf x i + vf x i gs x ts x fs x d x bclk x mclk x 8 khz adpcm out 20.48 mhz 1.544 mhz/ 2.048 mhz adcpm in powerdown + 5 v mc145554/57 mode ddo dde ddc ddi die pd /reset v ss v dd edo eoe edc edi eie spc adp mc145532 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 figure 3. adpcm transcoder application
mc145554 ? mc145557 ? MC145564 ? mc145567 motorola 13 mc33120 20 19 18 17 16 5 4 3 2 1 v cc bp cp tsi rsi cn bn en v ee v dd pdi /st2 st1 v dg v ag rxi rfo txo cf vqb mjd253 1n4002 1n4002 48 v 1 k 9.1 k 0.01 m f tip ring 100 1/4 w 48 v mjd243 15 12 13 14 9 10 8 11 7 6 + 5 v 5 m f, 16 v 48.5 k 4.7 k 20.6 k 47.4 k 1 m f 1.0 m f, 50 v 10 m f, 50 v 10 k 49.0 k 3 15 14 16 2 mc145554/7 v fro vf x i gs x vf x i+ gnda 1 13 6 11 9 8 7 10 5 12 4 8 khz sync data clock mc145554 = 1.544 mhz mc145557 = 2.048 mhz to pcm hwy v cc fs x fs r bclk x bclk r mclk r mclk x d x d r ts x v bb note: six resistors and two capacitors on the twowire side can be 5% tolerance. + 0.01 m f 50 v 100 1/4 w 1n4002 1n4002 9.1 k 1 k + ep + 1 m f + 5 v 5 v 50 v hook status/ fault indication 300 w 20 w figure 4. a complete single party channel unit using mc145554/57 pcm codecfilter and mc33120 slic
mc145554 ? mc145557 ? MC145564 ? mc145567 motorola 14 s interface 33 k aso transceiver mc145474p mc145488 lapd/lapb controller 17 2 21 20 2 3 6 19 30 pf 15.36 mhz v dd iset tx+ tx rx+ rx v ss xtal extal te/nt sync clk rx tx dreq dgrt sel clk rx tx irq reset 4 8 9 11 7 5 15 14 13 12 30 pf 52, 2, 9 60, 44 59, 45 55, 49 56, 48 47 46 50 53 57 54 58 v dd sync 0, 1 clk 0, 1 rx 0, 1 dreq 1 dgnt 1 scpe 1 scpe 0 scp clk scp txd scp rxd v ss 51, 36, 21 + 5 v 500 w 0.1 m f 3 15 14 16 2 codecfilter 4 12, 5 10, 7, 8, 9 11 6 13 1 mc145554p vf r o vf x i gs x vf x i+ gnda v cc fs x , fs r mclk, bclk d x d r ts x v bb 500 w handset rj1 1 + rcvr (white) + mic (red) rcvr (white) mic (blk) mpu bus + 5 v 5 v + 5 v + 5 v + 5 v + 5 v + 5 v 1 k w 10 11 12 13 14 15 16 17 18 19 20 22 23 24 25 26 8 7 6 5 4 3 1 68 67 66 65 64 63 62 61 42 43 27 28 29 30 31 32 33 34 36 37 38 39 40 41 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 own0 own1 mclk cs r/w as lds uds rst iack irq dtack berr br bg bgack + 5 v 10 + 5 v 1 k w 1 k w 1 k w 7 w 7 w 7 w 7 w 10 k w tx 0, 1 figure 5. isdn voice/data terminal
mc145554 ? mc145557 ? MC145564 ? mc145567 motorola 15 table 3. mulaw encodedecode characteristics chord number step decision decode number of steps size levels sign chord chord chord step step step step levels normalized encode normalized 1 2 3 4 5 6 7 8 digital code 8159 1 0 0 0 0 0 0 0 8031 7903 8 16 256 4319 1 0 0 0 1 1 1 1 4191 4063 7 16 128 2143 1 0 0 1 1 1 1 1 2079 2015 6 16 64 1055 1 0 1 0 1 1 1 1 1023 991 5 16 32 511 1 0 1 1 1 1 1 1 495 479 4 16 16 239 1 1 0 0 1 1 1 1 231 223 3 16 8 103 1 1 0 1 1 1 1 1 99 95 2 16 4 35 1 1 1 0 1 1 1 1 33 31 1 15 2 3 1 1 1 1 1 1 1 0 2 1 1 1 1 1 1 1 1 1 1 1 0 0 notes: 1. characteristics are symmetrical about analog zero with sign bit = 0 for negative analog values. 2. digital code includes inversion of all magnitude bits.
mc145554 ? mc145557 ? MC145564 ? mc145567 motorola 16 table 4. alaw encodedecode characteristics chord number step decision decode number of steps size levels sign chord chord chord step step step step levels normalized encode normalized 1 2 3 4 5 6 7 8 digital code 4096 1 0 1 0 1 0 1 0 4032 3968 7 16 128 2176 1 0 1 0 0 1 0 1 2112 2048 6 16 64 1088 1 0 1 1 0 1 0 1 1056 1024 5 16 32 544 1 0 0 0 0 1 0 1 528 512 4 16 16 272 1 0 0 1 0 1 0 1 264 256 3 16 8 136 1 1 1 0 0 1 0 1 132 128 2 16 4 68 1 1 1 1 0 1 0 1 66 64 1 32 2 2 1 1 0 1 0 1 0 1 1 0 notes: 1. characteristics are symmetrical about analog zero with sign bit = 0 for negative analog values. 2. digital code includes alternate bit inversion, as specified by ccitt .
mc145554 ? mc145557 ? MC145564 ? mc145567 motorola 17 package dimensions l suffix ceramic package case 62009 (mc145554/57) min min max max inches millimeters dim 19.05 6.10 e 0.39 1.40 0.23 e 0 0.39 19.55 7.36 4.19 0.53 1.77 0.27 5.08 15 0.88 0.750 0.240 e 0.015 0.055 0.009 e 0 0.015 0.770 0.290 0.165 0.021 0.070 0.011 0.200 15 0.035 1.27 bsc 2.54 bsc 7.62 bsc 0.050 bsc 0.100 bsc 0.300 bsc a b c d e f g j k l m n notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of lead when formed parallel. 4. dimension f may narrow to 0.76 (0.030) where the lead enters the ceramic body. d 16 pl j 16 pl seating plane 0.25 (0.010) t a m s 0.25 (0.010) t b m s 1 8 9 16 -a- -b- k c n g e f -t- m l p suffix plastic dip case 64808 (mc145554/57) notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. a b f c s h g d j l m 16 pl seating 1 8 9 16 k plane t m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01
mc145554 ? mc145557 ? MC145564 ? mc145567 motorola 18 dw suffix sog package case 751g02 (mc145554/57) dim min max min max inches millimeters a 10.15 10.45 0.400 0.411 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.50 0.90 0.020 0.035 g 1.27 bsc 0.050 bsc j 0.25 0.32 0.010 0.012 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 m b m 0.010 (0.25) notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. a b p 8x g 14x d 16x seating plane t s a m 0.010 (0.25) b s t 16 9 8 1 f j r x 45 m c k l suffix ceramic package case 73203 (MC145564/67) notes: 1. leads within 0.25 (0.010) diameter, true position at seating plane, at maximum material condition. 2. dimension l to center of leads when formed parallel. 3. dimensions a and b include meniscus. dim min max min max inches millimeters a 23.88 25.15 0.940 0.990 b 6.60 7.49 0.260 0.295 c 3.81 5.08 0.150 0.200 d 0.38 0.56 0.015 0.022 f 1.40 1.65 0.055 0.065 g 2.54 bsc 0.100 bsc h 0.51 1.27 0.020 0.050 j 0.20 0.30 0.008 0.012 k 3.18 4.06 0.125 0.160 l 7.62 bsc 0.300 bsc m 0 15 0 15 n 0.25 1.02 0.010 0.040 a 20 1 10 11 b f c seating plane d h g k n j m l
mc145554 ? mc145557 ? MC145564 ? mc145567 motorola 19 p suffix plastic dip case 73803 (MC145564/67) 1.070 0.260 0.180 0.022 0.070 0.015 0.140 15 0.040 1.010 0.240 0.150 0.015 0.050 0.008 0.110 0 0.020 25.66 6.10 3.81 0.39 1.27 0.21 2.80 0 0.51 27.17 6.60 4.57 0.55 1.77 0.38 3.55 15 1.01 0.050 bsc 0.100 bsc 0.300 bsc 1.27 bsc 2.54 bsc 7.62 bsc min min max max inches millimeters dim a b c d e f g j k l m n notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of lead when formed parallel. 4. dimension b does not include mold flash. -a- c k n e g f d 20 pl j 20 pl l m -t- seating plane 1 10 11 20 0.25 (0.010) t a m m 0.25 (0.010) t b m m b dw suffix sog package case 751d04 (MC145564/67) notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.150 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. a b 20 1 11 10 s a m 0.010 (0.25) b s t d 20x m b m 0.010 (0.25) p 10x j f g 18x k c t seating plane m r x 45 dim min max min max inches millimeters a 12.65 12.95 0.499 0.510 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.50 0.90 0.020 0.035 g 1.27 bsc 0.050 bsc j 0.25 0.32 0.010 0.012 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029
mc145554 ? mc145557 ? MC145564 ? mc145567 motorola 20 motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability , including without limitation consequential or incidental damages. at ypicalo parameters can and do vary in dif ferent applications. all operating parameters, including at ypicalso must be validated for each customer application by customer ' s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur . should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly , any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/af firmative action employer . how to reach us: usa/europe : motorola literature distribution; japan : nippon motorola ltd.; tatsumispdjldc, toshikatsu otsuki, p.o. box 20912; phoenix, arizona 85036. 18004412447 6f seibubutsuryucenter, 3142 tatsumi kotoku, tokyo 135, japan. 0335218315 mfax : rmf ax0@email.sps.mot.com t ouchtone (602) 2446609 hong kong : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, internet : http://designnet.com 51 ting kok road, tai po, n.t., hong kong. 85226629298 mc145554/d ?

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